In a communication application, a microcomputer receives data and forwards the data to multiple destinations. A central processing unit (CPU) of the microcomputer sequentially writes the data to send buffers each of which corresponds to each destination.
In the case of FIG. 10, a CPU 1 writes write data Dw to three resources 2-4 such as peripheral circuits. The CPU 1 sequentially outputs a write enable signal Sw and an address signal Sa to an address decoder 5. The address decoder 5 decodes the address signal Sa and sequentially outputs one of select signals S1-S3 corresponding to the resources 2-4, respectively, in accordance with the decoded address signal Sa. As shown in FIGS. 11 and 12, therefore, the CPU 1 serially writes the write data Dw to the resources 2-4. The serial writing processing may introduce a delay into the communication processing.
JP-2004-362176A discloses a technique to overcome the above problem. In JP-2004-362176A, a host I/F 101 and a sequence block 102 are interposed between a host computer 200 and functional blocks 103-105. The host computer 200 sets a parameter STA in the sequence block 102, when the host computer 200 writes data to the functional blocks 103-105. Then, the sequence block 102 writes the data to the functional blocks 103-105 in accordance with the parameter STA.
The technique shortens the processing time of the host computer 200. However, the sequence block 102 writes the data to the functional blocks 103-105 in a cycle similar to that shown in FIG. 12. Therefore, the technique cannot shorten the overall processing time.